One or more aspects relate, in general, to memory, and in particular, to static random access memory (SRAM).
Static random access memory cells are currently used in many application scenarios to store data. Speed of access is one parameter for such SRAM cells. When designing a multi-Gigahertz (GHz) SRAM, power consumption is one consideration without sacrificing performance in terms of frequency, width, i.e., word size, and depth, i.e., word count.
A strong contributor to power consumption is a word decoder that allows access to single words based on an incoming word address. The word decoder decodes a binary address into single word lines.
Physically, SRAMs usually get partitioned into multiple SRAM cell core regions to cope with the physical wiring length of the word lines as well as with the physical wiring length of the bit lines on the memory chip. Bit lines are used to read-out stored data and write data into the SRAM cells. Both may not exceed a certain physical length due to physical implications.
Today's decoders will send all their pre-decoded signals to the last decoding stage, in particular a word line driver, located at each core region. This means that all pre-decoded signals may be toggling at all word line drivers even if only one of them may be activated. Typically, this may result in unnecessary power consumption.
As power density increases with each CMOS (complementary metal-oxide semiconductor) technology node and logic demands for larger high frequency SRAMs continue to grow, this decoding scheme may no longer be suitable. It may result in reliability issues due to power supply, lifetime problems because of electro migration and performance impacts due to the high amount of capacitance (load) required to drive the lines.
There are several disclosures related to an SRAM array comprising multiple cell cores.
U.S. Pat. No. 8,130,588A1, incorporated herein by reference in its entirety, discloses a semiconductor memory device including a memory cell array arranged in rows and columns, a row decoder and a control circuit. The control circuit generates the internal clock signal so that the row decoder does not operate for a predetermined time in response to the chip select signal.
US 2012/0285664A1, incorporated herein by reference in its entirety, discloses a system and method for adjusting timing of memory access operations to a memory block. A controller may be adapted to adjust timing of a memory access operation to the memory block by extending a portion of a clock pulse to compensate for delay associated with the memory block.